Semiconductor device fabrication involves a series of patterned layers formed using photolithography masks. For semiconductor devices to perform properly, each patterned layer should be aligned as precisely as possible with other patterned layers in the device. In other words, the overlay misalignment and error should be minimized.
One alignment technique is known as the ATHENA (Advanced Technology using High order Enhancement of Alignment) mark alignment technique. Another alignment technique is known as the SMASH (Smart Alignment Sensor Hybrid) mark alignment technique. ATHENA marks are formed in the scribe line area provided between chips. In the ATHENA mark alignment technique, light is radiated onto the wafer. The radiated light is diffracted by the alignment marks, and the diffraction pattern is detected. The relative position of the wafer and the photolithography mask is then adjusted accordingly. The quality of the diffracted light from the alignment mark is a directly related to the structure of the alignment mark—i.e., the material, depth, dimensions, etc. of the alignment mark. Typically, each alignment mark comprises a topographical pattern, such a plurality of grooves and lands, which can be formed by, for example etching a controlled depth into wafer. Once the alignment mark is formed on a wafer, it will be used for position detection in subsequent processes.
However as the wafer undergoes the various patterned layer forming processes and steps, the integrity of the alignment mark on the wafer may be compromised. For example, some of the intermediate processing steps of forming circuit patterns on the wafer, such as chemical mechanical polishing (CMP) or deposition of thick or opaque layer, can damage or distort the alignment marks on the wafer, causing difficult detection of the alignment mark and, hence, misalignment or errors in aligning the various patterned layers of the semiconductor device.